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| M62392P/FP 8-bit 12ch I2C BUS D/A Converter with Buffer Amplifiers REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Description The M62392P/FP is a CMOS 12 channels D/A converter with output buffer amplifiers. It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I2C BUS. The output buffer amplifier employs AB class output with sinking and sourcing capability of more than 1.0 mA, and an output voltage range is nearly between ground and VrefU. Maximum 8 ICs can be connected to a bus by using three chip-select pins, so that it is possible to handle up to 96 channels. Features * I2C BUS serial data method * Wide output voltage range Nearly between ground and VrefU (0 to 5 V) * High output current drive capability over 1.0 mA * 2 setting voltage ranges by dual input pins for upper voltage references (VrefU1, U2) Application Conversion from digital data to analog control data for both consumer and industrial equipment. Gain control and automatic adjustment of display-monitor or CTV. Block Diagram CS0 CS1 CS2 VDD 24 23 22 21 VCC 20 AO6 19 AO5 18 AO4 17 AO3 16 AO2 15 AO1 14 VrefU2 GND 13 12 Chip select + - + - + - + - + - + - I2C BUS transceiver Address decoder 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R 8-bit latch 8-bit upper segment R-2R + - + - + - + - + - + - 1 R 2 SCL 3 SDA 4 AO7 5 AO8 6 AO9 7 AO10 8 AO11 9 AO12 10 11 VrefL VrefU1 REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 1 of 8 M62392P/FP Pin Arrangement M62392P/FP R SCL SDA AO7 AO8 AO9 AO10 AO11 AO12 VrefL VrefU1 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 CS0 23 CS1 22 CS2 21 VDD 20 VCC 19 AO6 18 AO5 17 AO4 16 AO3 15 AO2 14 AO1 13 VrefU2 (Top view) Outline: PRDP0024AA-A (24P4D) 24P2N-B Pin Description Pin No. 3 1 2 14 15 16 17 18 19 4 5 6 7 8 9 20 21 12 10 11 13 22 23 24 Pin Name SDA R SCL Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Ao9 Ao10 Ao11 Ao12 VCC VDD GND VrefL VrefU1 VrefU2 CS2 CS1 CS0 Function Serial data input terminal Reset signal input terminal Serial clock input terminal 8-bit D/A converter output terminal Analog power supply terminal Digital power supply terminal Analog and digital common GND D/A converter low level reference voltage input terminal D/A converter high level reference voltage input terminal 1 D/A converter high level reference voltage input terminal 2 Chip select data input terminal 2 Chip select data input terminal 1 Chip select data input terminal 0 REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 2 of 8 M62392P/FP Absolute Maximum Ratings Item Supply voltage Supply voltage D/A converter high level reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VrefU1, 2 Vin VO Pd Topr Tstg Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VCC + 0.3 465 (P) / 421 (FP) -20 to +85 -40 to +125 Unit V V V V V mW C C Electrical Characteristics Item Supply voltage Supply current Input leak current Output low voltage (SDA) Input low voltage Input high voltage Symbol VDD IDD IILK VOL VIL VIH Min 4.5 -- -10 -- -- 0.8 VDD Limits Typ 5.0 -- -- -- -- -- Max 5.5 1.0 10 0.4 0.2 VDD -- Unit V mA A V V V Conditions CLK = 1 MHz operation, IAO = 0 A VIN = 0 to VDD Isink = 3 mA Item Supply voltage Supply current D/A converter high level reference voltage input current D/A converter high level reference voltage range D/A converter low level reference voltage range Buffer amplifier output voltage range Buffer amplifier output drive range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitive load Buffer amplifier output impedance Symbol VCC ICC IrefU Min 4.5 -- -- Limits Typ 5.0 1.0 1.4 Max 5.5 3.0 3.0 Unit V mA mA Conditions CLK = 1 MHz operation, IAO = 0 A VrefU = 5 V, VrefL = 0 V Data condition: at maximum current The output dose not necessarily be the values within the reference voltage setting range. IAO = 100 A IAO = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V VCC = 5.5 V (15 mV/LSB) Without load (IAO = 0) VrefU VrefL VAO IAO SDL SL SZERO SFULL CO RO 3.5 GND 0.1 0.2 -1.0 -1.0 -1.5 -2.0 -2.0 -- -- -- -- -- -- -- -- -- -- -- -- 5.0 VCC VCC - 3.5 VCC - 0.1 VCC - 0.2 1.0 1.0 1.5 2.0 2.0 0.1 -- V V V V mA LSB LSB LSB LSB F REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 3 of 8 M62392P/FP I2C BUS Line Characteristics Item SCL clock frequency Time the bus must be free before a new transmission can start Hold time START condition. After this period, the first clock pulse is generated. Low period of the clock High period of the clock Setup time for START condition (only relevant for a repeated START condition) Hold time DATA Setup time DATA Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Setup time for STOP condition Note: Symbol fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Normal Mode Min Max 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.0 100 -- -- -- -- -- -- -- 1000 300 -- Unit kHz s s s s s s ns ns ns s Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns Max) of the falling edge of SCL. Timing Chart tR, tF tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW tHIGH Start Start Stop Start REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 4 of 8 M62392P/FP I2C BUS Format STA Slave address W A Sub address A DAC data A STP Digital Data Format * Slave Address First 1 0 0 1 A2 A1 Last A0 * Sub Address First X X X X S3 S2 S1 Last S0 (Slave address) Chip select data Don't care Last LSB Channel select data * DAC Data First MSB D7 D6 D5 D4 D3 D2 D1 D0 (1) Chip Select Data MSB A2 0 0 0 : 1 Note: A1 0 0 1 : 1 LSB A0 0 1 0 : 1 CS2 0 0 0 : 1 CS1 0 0 1 : 1 CS0 0 1 0 : 1 (2) Channel Select Data MSB S3 0 0 0 : 1 1 1 : 1 S2 0 0 0 : 0 1 1 : 1 S1 0 0 1 : 1 0 0 : 1 LSB S0 0 1 0 : 1 0 1 : 1 Channel Selection Don't care ch1 selection ch2 selection : ch11 selection ch12 selection Don't care : Don't care Lower 3 bits (A0, A1, A2) are a programmable address. This IC is accessed only when the lower 3 bits data of slave address coincide with the data of CS0 to CS2. (Refer to the upper table) (3) DAC Data First MSB D7 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D2 0 0 0 0 : 1 1 D1 0 0 1 1 : 1 1 Last LSB D0 0 1 0 1 : 0 1 DAC Output (VrefU - VrefL ) / 256 x 1 + VrefL (VrefU - VrefL ) / 256 x 2 + VrefL (VrefU - VrefL ) / 256 x 3 + VrefL (VrefU - VrefL ) / 256 x 4 + VrefL : (VrefU - VrefL ) / 256 x 255 + VrefL VrefU REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 5 of 8 M62392P/FP Timing Chart (Model) SDA 1 2 3 4 5 6 7 W A SCL R D/A output Start condition SDA 1 2 3 4 5 6 7 8 A SCL R D/A output SCL R D/A output Stop condition * Start condition: With SCL at high, SDA line goes from high to low * Stop condition: With SCL at high, SDA line goes from low to high (Under normal circumstances, SDA is changed when SCL is low) * Acknowledge bit: The receiving IC has to pull down SDA line whenever receive slave data. (The transmitting IC releases the SDA line just then transmit 8-bit data.) REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 6 of 8 M62392P/FP Precaution for Use M62392 have 5 terminals (VDD, VCC, VrefU1, VrefU2, VrefL) for input constant voltage at use. If ripple or spike is input these terminals, accuracy of D/A conversion is down. So, when use this device, please connect capacitor among each terminal to GND for stable D/A conversion. This IC's output amplifier has an advantage to capacitive load. So it's no problem at device action when connect capacitor (0.1 F Max) among output to GND for every noise eliminate. Purchase of Renesas's I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to I2C Standard Specification as defined by Philips. Application Example 5V 10 F 10 F 5V VDD CS2 Chip select data setting CS1 CS0 Reset signal R VrefU1 5V 10 F VCC AO1 AO2 AO3 AO4 AO5 AO6 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 Analog output terminals VrefU2 5V 10 F AO7 AO8 AO9 5V AO10 SCL MCU SDA GND VrefL AO11 AO12 10 F REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 7 of 8 M62392P/FP Package Dimensions 24P2N-B EIAJ Package Code SOP24-P-300-1.27 24 Plastic 24pin 300mil SOP JEDEC Code -- Weight(g) Lead Material Cu Alloy 13 e b2 HE E e1 Recommended Mount Pad Symbol F 1 12 A G D A2 e y b A1 x M A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 c z Z1 Detail G Detail F Dimension in Millimeters Min Nom Max 2.1 -- -- 0.2 0 0.1 1.8 -- -- 0.35 0.5 0.4 0.25 0.2 0.18 15.12 15.02 14.92 5.4 5.3 5.2 1.27 -- -- 8.42 8.12 7.82 0.7 0.5 0.3 1.41 -- -- -- -- 0.525 -- -- 0.675 -- -- 0.25 0.1 -- -- 0 10 -- 0.76 -- -- 7.62 -- -- 1.27 -- -- L1 JEITA Package Code P-DIP24-6.3x29.2-2.54 RENESAS Code PRDP0024AA-A Previous Code 24P4D MASS[Typ.] 1.6g 24 13 L 1 12 c *1 *2 D NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. A2 Reference Dimension in Millimeters Symbol A e SEATING PLANE *3 b3 bp *3 b2 e1 D E A A1 A2 bp b2 b3 c e L REJ03D0883-0300 Rev.3.00 Mar 25, 2008 Page 8 of 8 L A1 e1 E Min Nom Max 7.32 7.62 7.92 29.0 29.2 29.4 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 15 0 2.29 2.54 2.79 3.0 I2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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